1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a contact hole and a method of manufacturing the same.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) is conventionally well known as a semiconductor memory which is a type of semiconductor devices. FIG. 35 is a cross sectional view showing a conventional DRAM. Referring to FIG. 35, a cross sectional structure of the conventional DRAM will be described first.
In a memory cell portion of the conventional DRAM, an isolation region 102 is provided in a prescribed region at the main surface of a silicon substrate 101. Source/drain regions 106a, 106b and 106c are formed in an active region surrounded by isolation region 102. On a channel region between source/drain regions 106a, 106b, a gate electrode 104a is formed with a gate oxide film 103 therebetween. Gate electrodes 104b and 104c are formed spaced apart from gate electrode 104a by a prescribed distance. A TEOS oxide film 105 is formed to cover the top surfaces of gate electrodes 104a to 104c. A sidewall oxide film 107 is formed to be in contact with side surfaces of gate electrodes 104a to 104c and of TEOS oxide film 105.
A silicon nitride film 108 is formed to cover TEOS oxide film 105, sidewall oxide film 107, and source/drain regions 106a to 106c. An interlayer insulating film 109 is formed on silicon nitride film 108. A bit line contact hole 160 is formed in the region of silicon nitride film 108 and interlayer insulating film 109 located on source/drain region 106b. A bit line 110a is formed to be electrically connected to source/drain region 106b through bit line contact hole 160 and to extend on the top surface of interlayer insulating film 109.
An interlayer insulating film 111 is formed on bit line 110a and interlayer insulating film 109. A capacitor contact hole 161 is formed in the region of silicon nitride film 108 and interlayer insulating films 109, 111 located on source/drain region 106a. A doped polycrystalline silicon film 112 is formed to be electrically connected to source/drain region 106a through capacitor contact hole 161 and to extend on the top surface of interlayer insulating film 111. Doped polycrystalline silicon film 112 includes a vertical part 112a electrically connected to source/drain region 106a and filling contact hole 161, and a horizontal part 112b formed integrally with this vertical part 112a and serving as a capacitor lower electrode.
A sidewall 113 of a doped polycrystalline silicon film is formed to come into contact with both side end surfaces of horizontal part 112b and to extend vertically. Sidewall 113 also serves as the capacitor lower electrode. To cover the top surface of horizontal part 112b and the surface of sidewall 113, a capacitor upper electrode 115 is formed thereon with a capacitor dielectric film 114 therebetween. Capacitor upper electrode 115 includes a doped polycrystalline silicon film. Capacitor lower electrode 112b, 113, capacitor dielectric film 114, and capacitor upper electrode 115 constitute a capacitor. An interlayer insulating film 116 is formed to cover the capacitor. On the top surface of interlayer insulating film 116, metal interconnections 118 are formed spaced apart by a prescribed distance.
On the other hand, in a peripheral circuitry portion, source/drain regions 106d and 106e are formed spaced apart by a prescribed distance at the main surface of silicon substrate 101. On a channel region between source/drain regions 106d, 106e, a gate electrode 104e is formed with gate oxide film 103 therebetween. On the region separated from gate electrode 104e by source/drain region 106d, a gate electrode 104d is formed with gate oxide film 103 therebetween. TEOS oxide film 105 is formed on the top surfaces of gate electrodes 104d and 104e. Sidewall oxide film 107 is formed to come into contact with the side surfaces of gate electrodes 104d and 104e and of TEOS oxide film 105.
Interlayer insulating film 109 is formed to cover source/drain regions 106d, 106e, sidewall oxide film 107, and TEOS oxide film 105. A contact hole is formed in the region of interlayer insulating film 109 located on source/drain region 106d and in the region of interlayer insulating film 109 located on gate electrode 104e. Inside these contact holes, an interconnection layer 110b is formed to be electrically connected to source/drain region 106d and gate electrode 104e. Here, interconnection layer 110b may be connected to either one of source/drain region 106d or gate electrode 104e. Interlayer insulating film 111 is formed to cover interconnection layer 110b, and interlayer insulating film 116 is formed to cover this interlayer insulating film 111. A contact hole is formed in the region of interlayer insulating films 111 and 116 located on a side end of interconnection layer 110b. A metal interconnection 117 is formed to be electrically connected to interconnection layer 110b through the contact hole and to extend along interlayer insulating film 116.
FIG. 36 shows a top plan layout of the entire memory cell portion of the above described conventional DRAM. Referring to FIG. 36, in the memory cell portion of the conventional DRAM, gate electrodes 104a to 104c are formed to extend in parallel, spaced apart by a prescribed distance. In a direction perpendicular to gate electrodes 104a to 104c, bit lines 110a are formed to extend almost in parallel, spaced apart by a prescribed distance. Bit line 110a is connected to source/drain region 106b in an active region 170 through bit line contact hole 160. Doped polycrystalline silicon film 112 serving as the capacitor lower electrode is connected to source/drain region 106a in active region 170 through capacitor contact hole 161.
FIGS. 37 to 53 are cross sectional views illustrating a manufacturing process of the conventional DRAM shown in FIG. 35. Referring to FIGS. 37 to 53, the manufacturing process of the conventional DRAM will be described below.
First, isolation region 102 is formed at the main surface of silicon substrate 101 in the memory cell portion, as shown in FIG. 37. On the main surface of silicon substrate 101, gate oxide films 103 are formed spaced apart by a prescribed distance. Respective gate electrodes 104a, 104b and 104c are formed on gate oxide films 103. In the peripheral circuitry portion as well, gate electrodes 104d and 104e are respectively formed on gate oxide films 103. By ion-implanting an impurity into silicon substrate 101 while using gate electrodes 104a to 104e as a mask, source/drain regions 106a to 106e are formed.
TEOS oxide film 105 is formed on the top surfaces of gate electrodes 104a to 104e. Sidewall oxide film 107 is formed to come into contact with side surfaces of gate electrodes 104a to 104e and of TEOS oxide film 105. By ion-implanting an impurity into source/drain regions 106d and 106e again, while using sidewall oxide film 107 in the peripheral circuitry portion as a mask, source/drain regions 106d and 106e of the LDD structure are completed.
Then, silicon nitride film 108 as an etching stopper layer is formed to cover the entire memory cell portion as shown in FIG. 38. Interlayer insulating film 109 including a silicon oxide film is formed to cover silicon nitride film 108 and the entire peripheral circuitry portion.
Thereafter, contact holes 109a to 109c as shown in FIG. 39 are formed by photolithography and dry etching. In etching for forming contact hole 109a in the memory cell portion, silicon nitride film 108 serves as an etching stopper layer. Then, silicon nitride film 108 in contact hole 109a is removed by etching, and bit line contact hole 160 from the top surface of interlayer insulating film 109 to source/drain region 106b is formed as shown in FIG. 40. Thereafter, interconnection layer 110 of a tungsten polyside layer, for example, is formed as shown in FIG. 41. By patterning this interconnection layer 110, bit line 110a of the memory cell portion and interconnection layer 110b of the peripheral circuitry portion are formed as shown in FIG. 42.
Then, interlayer insulating film 111 is formed to cover the entire surface, as shown in FIG. 43. As shown in FIG. 44, a polycrystalline silicon film 150 is formed on interlayer insulating film 111, and then a TEOS oxide film 151 is formed on polycrystalline silicon film 150. Thereafter, an opening 151a is formed in a prescribed region of TEOS oxide film 151.
After a TEOS oxide film (not shown) is formed to cover TEOS oxide film 151 and opening 151a, TEOS oxide film 151 is subjected to anisotropic etching to form a sidewall film 152 as shown in FIG. 45. By using the sidewall film 152 as a mask and by etching polycrystalline silicon film 150 located under the sidewall film, an opening 150a which is smaller in diameter than opening 151a by thickness of two sidewalls 152 can be formed. By anisotropic etching of interlayer insulating films 111 and 109 located below through this opening 150a, capacitor contact hole 161 as shown in FIG. 46 is formed.
Thereafter, a resist 153 is filled inside capacitor contact hole 161. This resist 153 is provided to protect the surface of silicon substrate 101 located at the bottom of capacitor contact hole 161 when polycrystalline silicon film 150 is removed by etching in a subsequent process. Polycrystalline silicon 150 is removed while this resist 153 is provided. As shown in FIG. 47, doped polycrystalline silicon film 112 is then formed filling capacitor contact hole 161 and extending along the top surface of interlayer insulating film 111. A BPSG oxide film 154 is formed on doped polycrystalline silicon film 112.
Thereafter, BPSG oxide film 154 and doped polycrystalline silicon film 112 are patterned by photolithography and dry etching to obtain the shape of the memory cell portion as shown in FIG. 48. Then, a doped polycrystalline silicon film 113 as shown in FIG. 49 is formed to cover BPSG oxide film 154 and interlayer insulating film 111. By anisotropic etching of doped polycrystalline silicon film 113, a sidewall 113a of a doped polycrystalline silicon film as shown in FIG. 50 is formed. Thereafter, BPSG oxide film 154 is removed to obtain the shape as shown in FIG. 51.
Then, as shown in FIG. 52, capacitor dielectric film 114, and doped polycrystalline silicon film 115 serving as the capacitor upper electrode are formed to cover doped polycrystalline silicon film 112, sidewall 113a and interlayer insulating film 111. By patterning capacitor dielectric film 114 and doped polycrystalline silicon film 115, the capacitor structure is then obtained as shown in FIG. 53.
Thereafter, interlayer insulating film 116 is formed on interlayer insulating film 111 of the peripheral circuitry portion and on capacitor upper electrode 115 of the memory cell portion as shown in FIG. 35. A contact hole is formed in the region of interlayer insulating films 116 and 111 of the peripheral circuitry portion located on interconnection layer 110b. Then, metal interconnection 117 is formed filling the contact hole and extending along the top surface of interlayer insulating film 116. In the memory cell portion as well, metal interconnections 118 are formed spaced apart by a prescribed distance on interlayer insulating film 116. Thus, the conventional DRAM is formed.
In the conventional DRAM shown in FIG. 35, reduction in the memory cell portion area is required as a semiconductor device is integrated to a higher degree. In this case, capacitor contact hole 161 and bit line contact hole 160 have to be formed in a very small active region. To satisfy these requirements, a technique for opening a contact hole in a self-alignment manner has been required. As such a self aligned contact opening method, a contact opening method using a silicon nitride film as an etching stopper is conventionally well known.
In the conventional structure shown in FIG. 35, bit line contact hole 160 is formed by the above mentioned self aligned contact opening method of a silicon nitride film. Specifically, as shown in FIG. 38, silicon nitride film 108 is formed and thereafter interlayer insulating film 109 of a silicon oxide film is formed thereon. By etching the portion of interlayer insulating film 109 located over source/drain region 106b while using silicon nitride film 108 as the etching stopper layer as shown in FIG. 39, contact hole 109a is formed in a self-alignment manner. Thereafter, nitride film 108 in contact hole 109a is removed to form bit line contact hole 160 as shown in FIG. 40. Conventionally, the self-aligned contact opening method using silicon nitride film 108 has been used to form bit line contact hole 160.
However, such an opening method using silicon nitride film 108 as an etching stopper layer is applicable only to a contact hole having a smaller depth as contact hole 109a shown in FIG. 39 because of following reasons. That is, although a selection ratio of a silicon oxide film and a silicon nitride film (an etching rate of the silicon oxide film/an etching rate of the silicon nitride film) is approximately 30 in theory, etching progresses faster in a stepped part than in a flat part of silicon nitride film 108. Therefore, the selection ratio of the silicon nitride film to the silicon oxide film is reduced to approximately 10 to 15 in the stepped part.
When a contact hole having a larger depth (larger aspect ratio) like, for example, capacitor contact 161 is opened by using silicon nitride film 108 as an etching stopper layer while such a selection ratio is taken, it takes longer time to etch silicon nitride film 108 due to a process margin. Therefore, when a contact hole having a larger depth as capacitor contact hole 161 is opened, the stepped part of silicon nitride film 108 under the hole is completely scraped off and TEOS oxide film 105 located on gate electrode 104 is scraped off. Thus, that gate electrode 104c is exposed. When doped polycrystalline silicon film 112 serving as the capacitor lower electrode is formed in capacitor contact hole 161 in this case, doped polycrystalline silicon film 112 and gate electrode 104c undesirably cause a short circuit. Therefore, the self aligned opening method using silicon nitride film 108 has been adapted for forming bit line contact hole 160 having a smaller depth, and the diameter reduction process shown in FIGS. 44 to 46 has been used for forming capacitor contact hole 161.
In the above mentioned diameter reduction process, however, the number of steps is increased and the manufacturing process becomes complicated as compared with the self aligned opening method using a silicon nitride film stopper. Since reduction in contact diameter of capacitor contact hole 161 is required as a memory cell becomes smaller, it is technically difficult to form a contact hole having a larger depth and a smaller contact diameter as shown in FIG. 35.
Further, as the memory cell portion becomes smaller, the space between adjacent bit lines 110a shown in FIG. 36 becomes narrower. When the space between bit lines 110a is narrower, capacitance between bit interconnections (Cb) becomes larger, delaying data reading and writing. As a result, high speed access becomes difficult. In the conventional structure shown in FIG. 36, vertical part 112a of doped polycrystalline silicon film 112 is located between adjacent bit lines 110a. However, since the outer diameter of this vertical part 62a is small, it does not reduce capacitance between adjacent bit lines 110a.